## An Animated Introduction to Digital Logic Design - Animations

The series "An Animated Introduction to Digital Logic Design - Animations" contains the animations of figures found in the book "An Animated Introduction to Digital Logic Design" by John D. Carpinelli. The full text of the book can be found here: https://digitalcommons.njit.edu/oat/1/

### Animations from 2023

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Figure 10.1: Generic PAL cell implementing the function ac + a'bc', John D. Carpinelli

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Figure 10.3: Generic PLA cell implementing the function ac + a'bc'., John D. Carpinelli

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Figure 10.5: PLD model of an 8x2 ROM., John D. Carpinelli

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Figure 1.6: Conversion of decimal integer to binary, John D. Carpinelli

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Figure 1.7: Conversion of decimal fraction to binary, John D. Carpinelli

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Figure 1.8: Conversion of decimal number to base 5, John D. Carpinelli

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Figure 2.10: Truth table showing the associative property for the AND function., John D. Carpinelli

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Figure 2.11: Truth table showing the associative property for the OR function., John D. Carpinelli

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Figure 2.12: Truth table verifying the first De Morgan’s law., John D. Carpinelli

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Figure 2.13: Truth table verifying the first De Morgan’s law., John D. Carpinelli

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Figure 2.19: Truth table for q = a'bc' + ac with minterms shown., John D. Carpinelli

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Figure 2.20: Truth table for q = a'bc' + ac with maxterms shown., John D. Carpinelli

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Figure 2.21: Truth table for the function q with minterms and maxterms shown., John D. Carpinelli

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Figure 2.36: Final table for phase 2 of the final example function., John D. Carpinelli

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Figure 2.3.a: Truth tables verifying the commutativity of the AND function., John D. Carpinelli

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Figure 2.3.b: Truth tables verifying the commutativity of the OR function., John D. Carpinelli

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Figure 2.4: Truth table verifying the distributive property of AND over OR., John D. Carpinelli

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Figure 2.5: Truth table verifying the distributive property of OR over AND., John D. Carpinelli

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Figure 2.8: Truth table verifying the involution property., John D. Carpinelli

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Figure 2.9.a: Truth table verifying both forms of absorption., John D. Carpinelli

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Figure 2.9.b: Truth table verifying both forms of absorption., John D. Carpinelli

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Figure 3.17: Buffer logic symbol and truth table., John D. Carpinelli

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Figure 3.4: NOT gate: (a) Symbol; (b) Truth table., John D. Carpinelli

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Figure 4.10: 16 to 4 encoder constructed using 8 to 3 encoders., John D. Carpinelli

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Figure 4.16: 8 to 1 multiplexer (a) Truth table; (b) Internal design., John D. Carpinelli

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Figure 4.17: 8 to 1 multiplexer constructed using a 3 to 8 decoder., John D. Carpinelli

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Figure 4.18: (a) Generic 1 to 8 demultiplexer (b) Truth table., John D. Carpinelli

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Figure 4.1: Generic 3 to 8 decoder with values shown. (600 dpi)., John D. Carpinelli

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Figure 4.1: Generic 3 to 8 decoder with values shown. (600 dpi)., John D. Carpinelli

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Figure 4.28: 4-bit ripple adder., John D. Carpinelli

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Figure 4.2: Generic 3 to 8 decoder with enable and values shown., John D. Carpinelli

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Figure 4.32: Tri-state buffer logic symbol and truth table., John D. Carpinelli

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Figure 4.3: 4 to 16 decoder constructed using two 3 to 8 decoders., John D. Carpinelli

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Figure 4.4: 4 to 16 decoder constructed using 2 to 4 decoders., John D. Carpinelli

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Figure 4.8: Generic 8 to 3 encoder with values shown., John D. Carpinelli

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Figure 6.10: S-R Latch with Enable Signal., John D. Carpinelli

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Figure 6.12: D latch: (a) Excitation table; (b) Circuit design., John D. Carpinelli

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Figure 6.14: D latch input, output, and internal signal values., John D. Carpinelli

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Figure 6.20: J-K flip-flop: Leader-follower design., John D. Carpinelli

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Figure 7.13: 16-bit shift register constructed from two 8-bit shift registers., John D. Carpinelli

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Figure 7.16: 4-bit ripple counter – final design., John D. Carpinelli

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Figure 7.1: 8-bit positive edge-triggered register., John D. Carpinelli

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Figure 7.20: 4-bit up/down counter., John D. Carpinelli

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Figure 7.21: 4-bit synchronous upcounter., John D. Carpinelli

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Figure 7.27: is an animation-only figure that shows this complete sequence., John D. Carpinelli

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