Figure 7.18: Counter carry-out: (a) Circuit to generate CARRY; (b) Sample timing diagram setting CARRY = 1.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 7.18: Counter carry-out: (a) Circuit to generate CARRY; (b) Sample timing diagram setting CARRY = 1. The animation shows the timing diagram as the outputs change from 1110 to 1111 to 0000. CARRY is 1 while the output is 1111 and COUNT=1.

Recommended Citation

Carpinelli, John D., "Figure 7.18: Counter carry-out: (a) Circuit to generate CARRY; (b) Sample timing diagram setting CARRY = 1." (2023). An Animated Introduction to Digital Logic Design - Animations. 95.
https://digitalcommons.njit.edu/dld-animations/95

Creative Commons License

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