Figure 5.3.b and c: Implementing the function q=a'b'c'+a'bc'+a'bc+ab'c'+ab'c+abc' using a decoder: (a) Truth table; (b) Decoder circuit implementation; (c) Decoder circuit implementation using inverse function.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-24-2023

Description

Animation of figure 5.3.b and c.

Recommended Citation

Carpinelli, John D., "Figure 5.3.b and c: Implementing the function q=a'b'c'+a'bc'+a'bc+ab'c'+ab'c+abc' using a decoder: (a) Truth table; (b) Decoder circuit implementation; (c) Decoder circuit implementation using inverse function." (2023). An Animated Introduction to Digital Logic Design - Animations. 67.
https://digitalcommons.njit.edu/dld-animations/67

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