Figure 6.10: S-R Latch with Enable Signal.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 6.10: S-R Latch with Enable Signal. System inputs S and E are input to a 2-input AND gate which sends its output to input S of the S-R latch. System inputs R and E are input to a 2-input AND gate which sends its output to input R of the S-R latch. Initially, inputs S, R, and E are 0, and outputs Q'=0 and Q=1. The inputs to the S-R latch are both 0. Then S changes to 1 and all other signals remain unchanged. Next, E changes to 1, which causes the AND gate generating the input to S of the latch to change to 1. The outputs of the latch change to Q=1 and Q'=0. Then system input S changes to 0 and the latch input S also changes to 0. Finally, R changes to 1, input R of the latch changes to 1, and the latch outputs change to Q=0 and Q'=1.

Recommended Citation

Carpinelli, John D., "Figure 6.10: S-R Latch with Enable Signal." (2023). An Animated Introduction to Digital Logic Design - Animations. 79.
https://digitalcommons.njit.edu/dld-animations/79

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