Figure 3.20: ToBe + ToBe': (a) Circuit diagram; (b) Timing diagram with propagation delays.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-24-2023

Description

Animation of figure 3.20.

Recommended Citation

Carpinelli, John D., "Figure 3.20: ToBe + ToBe': (a) Circuit diagram; (b) Timing diagram with propagation delays." (2023). An Animated Introduction to Digital Logic Design - Animations. 48.
https://digitalcommons.njit.edu/dld-animations/48

Creative Commons License

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