Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-24-2023
Description
Figure 3.20: ToBe + ToBe': (a) Circuit diagram; (b) Timing diagram with propagation delays. The animation shows the input ToBe change from 1 to 0 and how values change within the circuit and timing diagram. For a brief time, both inputs to the OR gate are 0 due to the delay of the NOT gate.
Recommended Citation
Carpinelli, John D., "Figure 3.20: ToBe + ToBe': (a) Circuit diagram; (b) Timing diagram with propagation delays." (2023). An Animated Introduction to Digital Logic Design - Animations. 48.
https://digitalcommons.njit.edu/dld-animations/48
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
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