Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-24-2023
Description
Figure 4.16: 8 to 1 multiplexer (a) Truth table; (b) Internal design. The animation shows all possible values of inputs to the multiplexer and the output each set of input values generates.
Recommended Citation
Carpinelli, John D., "Figure 4.16: 8 to 1 multiplexer (a) Truth table; (b) Internal design." (2023). An Animated Introduction to Digital Logic Design - Animations. 58.
https://digitalcommons.njit.edu/dld-animations/58
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
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