Animations from 2023
Figure 10.1: Generic PAL cell implementing the function ac + a'bc', John D. Carpinelli
Figure 10.2: a⊕b⊕c: (a) Truth table; (b) Implementation using two cells of a PAL. The upper cell generates a'b'c+a'bc'+ab'c' and the lower cell generates the final function., John D. Carpinelli
Figure 10.3: Generic PLA cell implementing the function ac + a'bc'., John D. Carpinelli
Figure 10.5: PLD model of an 8x2 ROM., John D. Carpinelli
Figure 10.6: D flip-flop model of a 16x2 ROM. Buffer enable signals shown in green., John D. Carpinelli
Figure 10.9: D flip-flop model of a 16x2 ROM with chip enable and output enable signals., John D. Carpinelli
Figure 1.16: Gray codes: (a) 1-bit Gray code; (b) Reflecting the 1-bit code; (c) Adding leading bit to produce the 2-bit Gray code; (d) 3-bit Gray code, John D. Carpinelli
Figure 1.4: Converting 927.625 from binary to octal. Zeroes added to complete groups of three bits are shown in red, John D. Carpinelli
Figure 1.5: Converting 927.625 from binary to hexadecimal. Zeroes added to complete groups of four bits are shown in red., John D. Carpinelli
Figure 1.6: Conversion of decimal integer to binary, John D. Carpinelli
Figure 1.7: Conversion of decimal fraction to binary, John D. Carpinelli
Figure 1.8: Conversion of decimal number to base 5, John D. Carpinelli
Figure 2.10: Truth table showing the associative property for the AND function., John D. Carpinelli
Figure 2.11: Truth table showing the associative property for the OR function., John D. Carpinelli
Figure 2.12: Truth table verifying the first De Morgan’s law., John D. Carpinelli
Figure 2.13: Truth table verifying the first De Morgan’s law., John D. Carpinelli
Figure 2.19: Truth table for q = a'bc' + ac with minterms shown., John D. Carpinelli
Figure 2.20: Truth table for q = a'bc' + ac with maxterms shown., John D. Carpinelli
Figure 2.21: Truth table for the function q with minterms and maxterms shown., John D. Carpinelli
Figure 2.22: (a) A 2 × 2 Karnaugh map; (b) Truth table for the baseball function; (c) Karnaugh map with values for function W shown., John D. Carpinelli
Figure 2.31: Quine-McCluskey algorithm, phase 2, for the baseball example: (a) Initial table; (b) Table with essential prime implicants circled and rows and columns crossed out., John D. Carpinelli
Figure 2.32: Another Quine-McCluskey example: (a) Truth table for the function; (b) Table used by phase 1; (c) Generating prime implicants., John D. Carpinelli
Figure 2.33: Phase 2 of the Quine-McCluskey algorithm: (a) Initial table; (b) Table with essential prime implicants circled and rows and columns crossed out., John D. Carpinelli
Figure 2.35: Final example phase 1 table: (a) initial table; (b) Final table with prime implicants circled., John D. Carpinelli
Figure 2.35: Final example phase 1 table: (a) initial table; (b) Final table with prime implicants circled. Part 2, John D. Carpinelli
Figure 2.36: Final table for phase 2 of the final example function., John D. Carpinelli
Figure 2.38: Segment g of the BCD to 7-segment decoder: (a) Original Karnaugh map; (b) One possible final Karnaugh map with prime implicants shown., John D. Carpinelli
Figure 2.39: Phase 1 of the Quine-McCluskey algorithm to determine the function for g., John D. Carpinelli
Figure 2.39: Phase 1 of the Quine-McCluskey algorithm to determine the function for g. Part 2., John D. Carpinelli
Figure 2.3.a: Truth tables verifying the commutativity of the AND function., John D. Carpinelli
Figure 2.3.b: Truth tables verifying the commutativity of the OR function., John D. Carpinelli
Figure 2.40: Phase 2 of the Quine-McCluskey algorithm to determine the function for g., John D. Carpinelli
Figure 2.4: Truth table verifying the distributive property of AND over OR., John D. Carpinelli
Figure 2.5: Truth table verifying the distributive property of OR over AND., John D. Carpinelli
Figure 2.8: Truth table verifying the involution property., John D. Carpinelli
Figure 2.9.a: Truth table verifying both forms of absorption., John D. Carpinelli
Figure 2.9.b: Truth table verifying both forms of absorption., John D. Carpinelli
Figure 3.10: Implementing q = a'bc' + ac using Sum of Products: (a) Truth table; (b) Circuit to realize q using minterms., John D. Carpinelli
Figure 3.12: Implementing q = (a + b + c')(a' + b' + c') using Product of Sums: (a) Expanded truth table; (b) Circuit to realize q using maxterms., John D. Carpinelli
Figure 3.13.b: Implementing q = (a'b'c + abc)' using Sum of Products for inverse functions: (a) Truth table; (b) Circuit to realize q'; (c) Inverting the output to realize q., John D. Carpinelli
Figure 3.13.c: Implementing q = (a'b'c + abc)' using Sum of Products for inverse functions: (a) Truth table; (b) Circuit to realize q'; (c) Inverting the output to realize q., John D. Carpinelli
Figure 3.17: Buffer logic symbol and truth table., John D. Carpinelli
Figure 3.1: AND gates: (a) 2-input AND gate; (b) Truth table; (c) 3- and 4-input AND gates., John D. Carpinelli
Figure 3.20: ToBe + ToBe': (a) Circuit diagram; (b) Timing diagram with propagation delays., John D. Carpinelli
Figure 3.2: OR gates: (a) 2-input OR gate; (b) Truth table; (c) 3- and 4-input OR gates., John D. Carpinelli
Figure 3.3: XOR gates: (a) 2-input XOR gate; (b) Truth table; (c) 3- and 4-input XOR gates., John D. Carpinelli
Figure 3.4: NOT gate: (a) Symbol; (b) Truth table., John D. Carpinelli
Figure 3.5: NAND gates: (a) 2-input NAND gate; (b) Truth table; (c) 3- and 4-input NAND gates., John D. Carpinelli
Figure 3.6: NOR gates: (a) 2-input NOR gate; (b) Truth table; (c) 3- and 4-input NOR gates., John D. Carpinelli
Figure 3.7: XNOR gates: (a) 2-input XNOR gate; (b) Truth table; (c) 3- and 4-input XNOR gates., John D. Carpinelli
Figure 3.8: Implementing the function q = a'bc' + ac: (a) Original truth table; (b) Expanded truth table; (c) Digital logic circuit to implement this function., John D. Carpinelli
Figure 4.10: 16 to 4 encoder constructed using 8 to 3 encoders., John D. Carpinelli
Figure 4.14: 8 to 1 multiplexer: (a) Truth table; (b) Generic representation with values shown., John D. Carpinelli
Figure 4.15: (a) 16 to 1 multiplexer constructed using two 8 to 1 multiplexers; (b) Truth table., John D. Carpinelli
Figure 4.16: 8 to 1 multiplexer (a) Truth table; (b) Internal design., John D. Carpinelli
Figure 4.17: 8 to 1 multiplexer constructed using a 3 to 8 decoder., John D. Carpinelli
Figure 4.18: (a) Generic 1 to 8 demultiplexer (b) Truth table., John D. Carpinelli
Figure 4.19: 1 to 8 demultiplexer constructed using a 3 to 8 decoder: (a) Circuit diagram; (b) Truth table., John D. Carpinelli
Figure 4.1: Generic 3 to 8 decoder with values shown. (600 dpi)., John D. Carpinelli
Figure 4.1: Generic 3 to 8 decoder with values shown. (600 dpi)., John D. Carpinelli
Figure 4.23: Half adder: (a) Inputs and outputs; (b) Truth table; (c) Internal design., John D. Carpinelli
Figure 4.27: Successful addition using full adders., John D. Carpinelli
Figure 4.28: 4-bit ripple adder., John D. Carpinelli
Figure 4.2: Generic 3 to 8 decoder with enable and values shown., John D. Carpinelli
Figure 4.32: Tri-state buffer logic symbol and truth table., John D. Carpinelli
Figure 4.3: 4 to 16 decoder constructed using two 3 to 8 decoders., John D. Carpinelli
Figure 4.4: 4 to 16 decoder constructed using 2 to 4 decoders., John D. Carpinelli
Figure 4.8: Generic 8 to 3 encoder with values shown., John D. Carpinelli
Figure 5.10.b: 3-input OR function q=a+b+c: (a) Truth table; (b) Lookup ROM circuit; (c) ROM data., John D. Carpinelli
Figure 5.11.b: 3-input AND q=abc and OR q=a+b+c functions: (a) Truth table; (b) Lookup ROM circuit; (c) ROM data., John D. Carpinelli
Figure 5.12.a: 2-bit multiplier lookup ROM: (a) Lookup memory circuit; (b) ROM contents; (c) Calculating values using a grid., John D. Carpinelli
Figure 5.2.b: Implementing the function q=a'bc'+ab'c+abc using a decoder: (a) Truth table; (b) Decoder circuit implementation., John D. Carpinelli
Figure 5.6.b: q=abc: (a) Partitioned truth tables; (b) Final design using a 4 to 1 multiplexer., John D. Carpinelli
Figure 5.7.c: Function q: (a) Truth table; (b) Partitioned truth tables; (c) Implementation using a 4 to 1 multiplexer., John D. Carpinelli
Figure 5.8.c: Function q: (a) Truth table; (b) Partitioned truth tables using b and c as multiplexer select inputs; (c) Implementation using a 4 to 1 multiplexer., John D. Carpinelli
Figure 5.9.b: 3-input AND function q=abc: (a) Truth table; (b) Lookup ROM circuit; (c) ROM data., John D. Carpinelli
Figure 6.10: S-R Latch with Enable Signal., John D. Carpinelli
Figure 6.11: D Latch: (a) Truth table; (b) Excitation table with S and R input values; (c) Circuit design., John D. Carpinelli
Figure 6.12: D latch: (a) Excitation table; (b) Circuit design., John D. Carpinelli
Figure 6.14: D latch input, output, and internal signal values., John D. Carpinelli
Figure 6.16: D flip-flop: (a) Leader-follower design; (b) Signal values for sample input sequence., John D. Carpinelli
Figure 6.18: Internal design of the positive edge-triggered D flip-flop with preset and clear., John D. Carpinelli
Figure 6.20: J-K flip-flop: Leader-follower design., John D. Carpinelli
Figure 6.21: Creating a J-K flip-flop using a D flip-flop: (a) Excitation table; (b) Karnaugh map to generate D; (c) Final circuit., John D. Carpinelli
Figure 6.2: Block diagram of a circuit that outputs 1 when three 1’s have been input., John D. Carpinelli
Figure 6.7: S-R Latch: (a) Internal configuration using NOR gates; (b) Truth table., John D. Carpinelli
Figure 6.8: S-R Latch: (a) Internal configuration using NAND gates; (b) Truth table., John D. Carpinelli
Figure 6.9: S-R Latch: (a) Internal configuration using NAND gates; (b) Truth table., John D. Carpinelli
Figure 7.13: 16-bit shift register constructed from two 8-bit shift registers., John D. Carpinelli
Figure 7.16: 4-bit ripple counter – final design., John D. Carpinelli
Figure 7.1: 8-bit positive edge-triggered register., John D. Carpinelli
Figure 7.18: Counter carry-out: (a) Circuit to generate CARRY; (b) Sample timing diagram setting CARRY = 1., John D. Carpinelli
Figure 7.20: 4-bit up/down counter., John D. Carpinelli
Figure 7.21: 4-bit synchronous upcounter., John D. Carpinelli
Figure 7.27: is an animation-only figure that shows this complete sequence., John D. Carpinelli
Figure 7.2: 8-bit register with LOAD: (a) Generic diagram showing inputs and outputs; (b) Example timing diagram., John D. Carpinelli
