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An Animated Introduction to Digital Logic Design - Animations

The series "An Animated Introduction to Digital Logic Design - Animations" contains the animations of figures found in the book "An Animated Introduction to Digital Logic Design" by John D. Carpinelli. The full text of the book can be found here: https://digitalcommons.njit.edu/oat/1/

Animations from 2023 2023

Figure 7.30: Synchronous BCD counter., John D. Carpinelli

Figure 7.32: Timing diagram for the BCD counter with transient 1010 output., John D. Carpinelli

Figure 7.5: 8-bit linear shift right register constructed using D flip-flops., John D. Carpinelli

Figure 7.6: 8-bit linear shift register relabeled for linear shift left operation., John D. Carpinelli

Figure 7.7: Linear shift register constructed using J-K flip-flops: (a) Excitation table; (b) Final design., John D. Carpinelli

Figure 7.9: Bidirectional shift register constructed using D flip-flops and multiplexers, color coded as follows: RED = direction of shift (0=left, 1=right); GREEN = data paths for left shift; PURPLE = data paths for right shift; BLACK = clock and data path from multiplexers to flip-flops., John D. Carpinelli

Figure 8.12: Moore machine state table for the D flip-flop., John D. Carpinelli

Figure 8.13: Moore machine for the 1’s counter that outputs 1 until the next sequence begins: (a) State diagram; (b) State table., John D. Carpinelli

Figure 8.29: Reduced state table and functions for system outputs., John D. Carpinelli

Figure 8.30: Final circuit for the 3-bit Gray code sequence generator using a counter., John D. Carpinelli

Figure 8.33: Final circuit for the 3-bit Gray code sequence generator using a counter and a decoder., John D. Carpinelli

Figure 8.34: Generic state machine constructed using a lookup ROM., John D. Carpinelli

Figure 8.37: Animation of the ROM-based 3-bit Gray code sequence generator., John D. Carpinelli

Figure 8.44: Final state diagram and state table after combining S2 and S4., John D. Carpinelli

Figure 8.47: Completed implication table., John D. Carpinelli

Figure 8.49: Completed timing diagram for the 1’s counter., John D. Carpinelli

Figure 8.4: D flip-flop state table, excluding output values., John D. Carpinelli

Figure 8.7: Mealy machine state table for the D flip-flop., John D. Carpinelli

Figure 9.19: Example of a static-1 hazard: (a) Circuit; (b) Timing diagram., John D. Carpinelli

Figure 9.20: Example of a static-0 hazard: (a) Circuit; (b) Timing diagram., John D. Carpinelli

Figure 9.22: Timing diagram illustrating the static-1 hazard., John D. Carpinelli

Figure 9.24: Timing diagram showing the static-1 hazard has been resolved., John D. Carpinelli

Figure 9.27: Timing diagram showing the static-0 hazard., John D. Carpinelli

Figure 9.28: (a) Karnaugh map; (b) updated circuit; and (c) timing diagram with static-0 hazard removed., John D. Carpinelli

Figure 9.29: (a) Circuit with a dynamic hazard, and (b) its timing diagram., John D. Carpinelli

Figure 9.30: Transition table with non-critical race conditions., John D. Carpinelli

Figure 9.31: Transition table with a critical race condition., John D. Carpinelli

Figure 9.5: S-R latch in a stable state., John D. Carpinelli

Figure 9.6: Transition from (a) a transient state to (b) a stable state., John D. Carpinelli

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