Figure 6.11: D Latch: (a) Truth table; (b) Excitation table with S and R input values; (c) Circuit design.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 6.11: D Latch: (a) Truth table; (b) Excitation table with S and R input values; (c) Circuit design. The circuit consists of an S-R latch, D is input directly to S; D is passed through a NOT gate and input to R. Initially, D=0, Q=0, and Q'=1. Then D changes to 1. The inputs of the latch change to S=1 and R=0, and the outputs change to Q=1 and Q'=0.

Recommended Citation

Carpinelli, John D., "Figure 6.11: D Latch: (a) Truth table; (b) Excitation table with S and R input values; (c) Circuit design." (2023). An Animated Introduction to Digital Logic Design - Animations. 80.
https://digitalcommons.njit.edu/dld-animations/80

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