Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-26-2023
Description
Figure 6.12: D latch: (a) Excitation table; (b) Circuit design. System inputs D and E are input to a 2-input AND gate which sends its output to input S of the S-R latch. System inputs D passed through a NOT gate and E are input to a 2-input AND gate which sends its output to input R of the S-R latch. Initially, inputs D and E are 0 and 1, respectively, and outputs Q'=1 and Q=0. The inputs to the S-R latch are 0 and 1, respectively. Then D changes to 1 and the inputs to the latch change to S=1 and R=0. The outputs change to Q=1 and Q'=0. Next, E changes to 0 and input S changes to 0; all other signals remain unchanged. Next, D changes to 0 and all other signal remain unchanged. Then E changes to 1, which causes the AND gate generating the input to R of the latch to change to 1. The outputs of the latch change to Q=0 and Q'=1.
Recommended Citation
Carpinelli, John D., "Figure 6.12: D latch: (a) Excitation table; (b) Circuit design." (2023). An Animated Introduction to Digital Logic Design - Animations. 81.
https://digitalcommons.njit.edu/dld-animations/81
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