Figure 10.2: a⊕b⊕c: (a) Truth table; (b) Implementation using two cells of a PAL. The upper cell generates a'b'c+a'bc'+ab'c' and the lower cell generates the final function.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 10.2: a⊕b⊕c: (a) Truth table; (b) Implementation using two cells of a PAL. The upper cell generates a'b'c+a'bc'+ab'c' and the lower cell generates the final function. The animation shows all possible values of a, b, and c, and the outputs of each gate in the circuit for each set of input values.

Recommended Citation

Carpinelli, John D., "Figure 10.2: a⊕b⊕c: (a) Truth table; (b) Implementation using two cells of a PAL. The upper cell generates a'b'c+a'bc'+ab'c' and the lower cell generates the final function." (2023). An Animated Introduction to Digital Logic Design - Animations. 125.
https://digitalcommons.njit.edu/dld-animations/125

Creative Commons License

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