Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-24-2023
Description
Figure 4.17: 8 to 1 multiplexer constructed using a 3 to 8 decoder. The animation shows the portion of the multiplexer that is actually a decoder and converts the design to use a decoder within the circuit. It then shows all possible values of the inputs and the output generated by each set of input values.
Recommended Citation
Carpinelli, John D., "Figure 4.17: 8 to 1 multiplexer constructed using a 3 to 8 decoder." (2023). An Animated Introduction to Digital Logic Design - Animations. 59.
https://digitalcommons.njit.edu/dld-animations/59
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
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