Figure 6.14: D latch input, output, and internal signal values.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 6.14: D latch input, output, and internal signal values. The animation shows the timing diagram and the circuit, with the values of each signal and the portion of the timing diagram being realized shown in red. Initially, D, E, S, R, and Q are 0 and Q' is 1. Then E changes to 1, which sets R to 1, Q to 1, and Q- to 0. Next, D is set to 1, which sets S=1, R=0, Q=1, and Q'=0. Then D is set to 0, and S=0, R=1, Q=0, and Q'=1. Next, D is again set to 1, which sets S=1, R=0, Q=1, and Q'=0. Finally, E is set to 0, which sets S=0 and R=0. The outputs are unchanged. Finally, D is set to 0 and no other signals change values.

Recommended Citation

Carpinelli, John D., "Figure 6.14: D latch input, output, and internal signal values." (2023). An Animated Introduction to Digital Logic Design - Animations. 82.
https://digitalcommons.njit.edu/dld-animations/82

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