Figure 6.21: Creating a J-K flip-flop using a D flip-flop: (a) Excitation table; (b) Karnaugh map to generate D; (c) Final circuit.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 6.21: Creating a J-K flip-flop using a D flip-flop: (a) Excitation table; (b) Karnaugh map to generate D; (c) Final circuit. The final circuit is a D flip-flop with input D connected to the output of a 2-input OR gate. The inputs of the OR gate are connected to two 2-input AND gates. The first AND gate has inputs J and output Q' of the flip-flop. The inputs to the second AND gate are connected to K passed through a NOT gate and output Q of the flip-flop. Outputs Q and Q' of the flip-flop are labeled Q and Q', respectively. Initially, J=L=CLK=0 and the outputs of the D flip-flop are Q=0 and Q'=1. CLK changes to 1 and back to 0; no other signals change values. Then J and K change to 1. When CLK changes to 1, the outputs become Q=1 and Q'=0. Then CLK changes to 0 and no other signals change values. Next, J become 0. When CLK changes from 0 to 1, the outputs change to Q=0 and Q'=1. Then CLK changes to 0 and no other signals change values. Following this, J becomes 1 and K becomes 0. When CLK changes to 1, the outputs change to Q=1 and Q'=0. CLK changes to 0 and no other signals change values. Finally, K changes to 1 and no other signals change values. When CLK changes from 0 to 1, the outputs change to Q=0 and Q'=1.

Recommended Citation

Carpinelli, John D., "Figure 6.21: Creating a J-K flip-flop using a D flip-flop: (a) Excitation table; (b) Karnaugh map to generate D; (c) Final circuit." (2023). An Animated Introduction to Digital Logic Design - Animations. 86.
https://digitalcommons.njit.edu/dld-animations/86

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