Figure 5.2.b: Implementing the function q=a'bc'+ab'c+abc using a decoder: (a) Truth table; (b) Decoder circuit implementation.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-24-2023

Description

Figure 5.2: Implementing the function q=a'bc'+ab'c+abc using a decoder: (a) Truth table; (b) Decoder circuit implementation. The animation shows all possible combinations of input values and the decoder and OR gate values they produce.

Recommended Citation

Carpinelli, John D., "Figure 5.2.b: Implementing the function q=a'bc'+ab'c+abc using a decoder: (a) Truth table; (b) Decoder circuit implementation." (2023). An Animated Introduction to Digital Logic Design - Animations. 66.
https://digitalcommons.njit.edu/dld-animations/66

Creative Commons License

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