Figure 6.8: S-R Latch: (a) Internal configuration using NAND gates; (b) Truth table.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 6.8: S-R Latch: (a) Internal configuration using NAND gates; (b) Truth table. Initially, S=R=0, Q'=0, and Q=1. Then input R changes to 1, which sets Q'=1 and Q=0. Next, R changes back to 0, and the outputs remain unchanged. Then S changes to 1, which sets Q'=0 and Q=1. Then S changes to 0 and the outputs remain unchanged. Finally, both S and R change to 1, which sets both outputs to 1.

Recommended Citation

Carpinelli, John D., "Figure 6.8: S-R Latch: (a) Internal configuration using NAND gates; (b) Truth table." (2023). An Animated Introduction to Digital Logic Design - Animations. 77.
https://digitalcommons.njit.edu/dld-animations/77

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