Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
Error loading player: No playable sources found
Publication Date
6-26-2023
Description
Figure 7.16: 4-bit ripple counter – final design. Initially the flip-flop outputs are 1110. When CLK changes from 0 to 1, the output changes to 1111. When CLK changes back to 0 and back to 1 again, the outputs change to 0000.
Recommended Citation
Carpinelli, John D., "Figure 7.16: 4-bit ripple counter – final design." (2023). An Animated Introduction to Digital Logic Design - Animations. 94.
https://digitalcommons.njit.edu/dld-animations/94
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
COinS
