Figure 7.16: 4-bit ripple counter – final design.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 7.16: 4-bit ripple counter – final design. Initially the flip-flop outputs are 1110. When CLK changes from 0 to 1, the output changes to 1111. When CLK changes back to 0 and back to 1 again, the outputs change to 0000.

Recommended Citation

Carpinelli, John D., "Figure 7.16: 4-bit ripple counter – final design." (2023). An Animated Introduction to Digital Logic Design - Animations. 94.
https://digitalcommons.njit.edu/dld-animations/94

Creative Commons License

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