Figure 10.5: PLD model of an 8x2 ROM.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 10.5: PLD model of an 8x2 ROM. The animation the outputs of each gate in the circuit for input values A2-A1-A0 = 1-0-0.

Recommended Citation

Carpinelli, John D., "Figure 10.5: PLD model of an 8x2 ROM." (2023). An Animated Introduction to Digital Logic Design - Animations. 127.
https://digitalcommons.njit.edu/dld-animations/127

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