Figure 6.2: Block diagram of a circuit that outputs 1 when three 1’s have been input.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 6.2: Block diagram of a circuit that outputs 1 when three 1’s have been input. The clock input oscillates between 0 and 1, and the input value alternates between 0 and 1 every other clock cycle. The timing diagram hows the output change from 0 to 1 on the risting edge of the clock the third time a 1 is read in at the input.

Recommended Citation

Carpinelli, John D., "Figure 6.2: Block diagram of a circuit that outputs 1 when three 1’s have been input." (2023). An Animated Introduction to Digital Logic Design - Animations. 75.
https://digitalcommons.njit.edu/dld-animations/75

Creative Commons License

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