Figure 7.2: 8-bit register with LOAD: (a) Generic diagram showing inputs and outputs; (b) Example timing diagram.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 7.2: 8-bit register with LOAD: (a) Generic diagram showing inputs and outputs; (b) Example timing diagram. The animation shows progression through the timing diagram. When LOAD = 1 and CLK changes from 0 to 1, the Q outputs change from 01010011 to 10111100.

Recommended Citation

Carpinelli, John D., "Figure 7.2: 8-bit register with LOAD: (a) Generic diagram showing inputs and outputs; (b) Example timing diagram." (2023). An Animated Introduction to Digital Logic Design - Animations. 88.
https://digitalcommons.njit.edu/dld-animations/88

Creative Commons License

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