Figure 9.24: Timing diagram showing the static-1 hazard has been resolved.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 9.24: Timing diagram showing the static-1 hazard has been resolved. Initially, a and c are 1, b is 0, and Q is 1. Then a becomes 0. After a delay, the output of the middle AND gate becomes 0. After a greater delay, the output of the lower AND gate becomes 1. During this time, the output of the upper AND gate remains 1, as does output Q.

Recommended Citation

Carpinelli, John D., "Figure 9.24: Timing diagram showing the static-1 hazard has been resolved." (2023). An Animated Introduction to Digital Logic Design - Animations. 118.
https://digitalcommons.njit.edu/dld-animations/118

Creative Commons License

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