Figure 9.29: (a) Circuit with a dynamic hazard, and (b) its timing diagram.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 9.29: (a) Circuit with a dynamic hazard, and (b) its timing diagram. Initially, B is 1, B1' and B2' are 0, the output of the OR gate is 1, and Q is 0. Then B changes to 0. After a delay, B2' changes to 1. For a brief time, both inputs to the AND gate are 1 and Q becomes 1. After a delay, the output of the OR gate changes to 0 and then Q changes back to 0. Then B1' changes to 1, the output of the OR gate changes to 1, and the Q changes back to 1.

Recommended Citation

Carpinelli, John D., "Figure 9.29: (a) Circuit with a dynamic hazard, and (b) its timing diagram." (2023). An Animated Introduction to Digital Logic Design - Animations. 121.
https://digitalcommons.njit.edu/dld-animations/121

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