Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
Publication Date
6-26-2023
Description
Figure 9.28: (a) Karnaugh map; (b) updated circuit; and (c) timing diagram with static-0 hazard removed. Initially, a and c are 0, b is 1, and Q is 0. Then a becomes 1. After a delay, the output of the upper OR gate becomes 1. After a greater delay, the output of the second OR gate becomes 1. During this time, the output of the lower OR gate remains 0, as does output Q.
Recommended Citation
Carpinelli, John D., "Figure 9.28: (a) Karnaugh map; (b) updated circuit; and (c) timing diagram with static-0 hazard removed." (2023). An Animated Introduction to Digital Logic Design - Animations. 120.
https://digitalcommons.njit.edu/dld-animations/120
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
