Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
Publication Date
6-26-2023
Description
Figure 9.22: Timing diagram illustrating the static-1 hazard. Initially, a and c are 1, b is 0, and Q is 1. Then a becomes 0. After a delay, the output of the upper AND gate becomes 0. After a greater delay, the output of the second AND gate becomes 1. During this second delay, both inputs to the OR gate are briefly 0 and its output changes to 0 and then back to 1.
Recommended Citation
Carpinelli, John D., "Figure 9.22: Timing diagram illustrating the static-1 hazard." (2023). An Animated Introduction to Digital Logic Design - Animations. 117.
https://digitalcommons.njit.edu/dld-animations/117
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
