Figure 9.20: Example of a static-0 hazard: (a) Circuit; (b) Timing diagram.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 9.20: Example of a static-0 hazard: (a) Circuit; (b) Timing diagram. Initially, ToBe is 0 and Q is 0, and the output of the NOT gate (ToBe') is 1. Then ToBe becomes 1. After a delay, ToBe' becomes 0. During the delay time, both inputs to the AND gate are 1 and Q briefly changes to 1 and then back to 0.

Recommended Citation

Carpinelli, John D., "Figure 9.20: Example of a static-0 hazard: (a) Circuit; (b) Timing diagram." (2023). An Animated Introduction to Digital Logic Design - Animations. 116.
https://digitalcommons.njit.edu/dld-animations/116

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