Figure 9.19: Example of a static-1 hazard: (a) Circuit; (b) Timing diagram.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 9.19: Example of a static-1 hazard: (a) Circuit; (b) Timing diagram. Initially, ToBe is 1 and Q is 1, and the output of the NOT gate (ToBe') is 0. Then ToBe becomes 0. After a delay, ToBe' becomes 1. During the delay time, both inputs to the OR gate are 0 and Q briefly changes to 0 and then back to 1.

Recommended Citation

Carpinelli, John D., "Figure 9.19: Example of a static-1 hazard: (a) Circuit; (b) Timing diagram." (2023). An Animated Introduction to Digital Logic Design - Animations. 115.
https://digitalcommons.njit.edu/dld-animations/115

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