Document Type

Thesis

Date of Award

12-31-2025

Degree Name

Master of Science in Computer Engineering - (M.S.)

Department

Electrical and Computer Engineering

First Advisor

Shaahin Angizi

Second Advisor

Dong Kyun Ko

Third Advisor

Anirudh Sridhar

Abstract

Modern DRAM scaling has reduced cell capacitance and increased thermal sensitivity, making disturbance-based faults such as RowHammer and RowPress increasingly significant reliability and security concerns. RowHammer induces bit flips through repeated row activations, while RowPress does so by holding a wordline open for an extended duration; both exploit inherent capacitive coupling and leakage mechanisms in dense DRAM arrays. This thesis introduces HeatHammer, a thermally assisted disturbance exploit that interleaves RowPress and RowHammer operations to amplify charge leakage and trigger row-traversing bit flips. Using the FPGA-based DRAM-Bender test platform, HeatHammer is evaluated on four commercially available DDR4 modules from different manufacturers under controlled thermal cycling. Experimental results demonstrate that elevated temperature significantly increases both disturbance strength and the distance over which bit flips can occur. Certain modules exhibits hundreds of row-traversing bit flips at 50°C, while others show minimal traversal but heightened retention-related failures, revealing substantial architectural and fabrication-dependent variation. These observations further highlight limitations in existing mitigation mechanisms, including Target Row Refresh (TRR), which remains insufficient under thermal stress. Overall, this work provides the first systematic characterization of the HeatHammer exploit and underscores the need for thermally aware reliability modeling and more robust, next-generation disturbance-mitigation strategies as DRAM technology continues to scale.

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