Figure 9.27: Timing diagram showing the static-0 hazard.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 9.27: Timing diagram showing the static-0 hazard. Initially, a and c are 0, b is 1, and Q is 0. Then a becomes 1. After a delay, the output of the upper OR gate becomes 1. After a greater delay, the output of the second OR gate becomes 1. During this second delay, both inputs to the AND gate are briefly 1 and its output changes to 1 and then back to 0.

Recommended Citation

Carpinelli, John D., "Figure 9.27: Timing diagram showing the static-0 hazard." (2023). An Animated Introduction to Digital Logic Design - Animations. 119.
https://digitalcommons.njit.edu/dld-animations/119

Creative Commons License

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