Document Type
Thesis
Date of Award
Spring 5-31-2000
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
William N. Carr
Second Advisor
Roy H. Cornely
Third Advisor
Edip Niver
Abstract
The objective of this thesis is to design a programmable wafer testing array on a single chip based on micro electromechanical systems (MEMS) and VLSI. The wafer-scale integration in this thesis is a programmable array of test probes that are used for engineering test of VLSI and ULSI silicon integrated circuits at the wafer level. This consists of two subsystems (1) the VLSI address circuits used for addressing and controlling the MEMS on the chip and (2) the latching probe MEMS microstructure array that actuates into position for testing VLSI wafers. Each of the subsystems have been designed, analyzed and simulated separately. These structures were then integrated into a demonstration 4x4 array forming a programmable probe card. A 3-micrometer critical dimension is used for both the VLSI CMOS and the MEMS physical design layouts. The fabrication technique for the MEMS microstructure is detailed. A standard 12-mask CMOS technology is used for the fabrication of the address circuits.
Recommended Citation
Sadeq, Salima Taifa, "Programmable latching probe microstructures for wafer testing applications" (2000). Theses. 760.
https://digitalcommons.njit.edu/theses/760
