Document Type
Thesis
Date of Award
Summer 8-31-2002
Degree Name
Master of Science in Materials Science and Engineering - (M.S.)
Department
Committee for the Interdisciplinary Program in Materials Science and Engineering
First Advisor
N. M. Ravindra
Second Advisor
Anthony Fiory
Third Advisor
Dentcho V. Ivanov
Fourth Advisor
Sufian Abedrabbo
Abstract
Semiconductors are the burgeoning industries in today's information age. Silicon based microelectronic devices are shrinking day-by-day in accord with the scaling dimensions reported by the International Technology Roadmap for Semiconductors (ITRS). There have been many semiconductor models and simulation programs constantly keeping pace with the continuously evolving scaling dimensions, process technology, performance and cost. Electrical characterization plays a vital role in determining the electrical properties of materials and device structures. Silicon based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) forms the basis of Complimentary Metal Oxide Semiconductor (CMOS) circuits. Today's aggressive scaling approaches in silicon Integrated Circuit (IC) technology require ultra shallow junctions in MOSFETs.
The objective of this thesis is to study the leakage current in n/p shallow junctions and to correlate them with process steps required for the formation of shallow junctions. The leakage current measurements were performed by utilizing three-point probe method, which is one of the popular techniques used in the semiconductor industry. Apart from n/p shallow junctions, experiments have been performed on p/n shallow junctions. Finally, comparison of the leakage current measurements has been made. The comparison takes into account the implant variables and post-implant annealing steps that have been deployed in the fabrication of shallow junctions.
Recommended Citation
Madishetty, Sridhar, "Formation and characterization of n/p shallow junctions in sub-micron MOSFETs" (2002). Theses. 694.
https://digitalcommons.njit.edu/theses/694
