Document Type
Thesis
Date of Award
Spring 5-31-2003
Degree Name
Master of Science in Computer Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Sotirios Ziavras
Second Advisor
Edwin Hou
Third Advisor
Alexandros V. Gerbessiotis
Abstract
Solving a system of linear equations is a key problem in the field of engineering and science. Matrix factorization is a key component of many methods used to solve such equations. However, the factorization process is very time consuming, so these problems have traditionally been targeted for parallel machines rather than sequential ones. Nevertheless, commercially available supercomputers are expensive and only large institutions have the resources to purchase them or use them. Hence, efforts are on to develop more affordable alternatives. This thesis presents one such approach.
The work presented here is an implementation of a parallel version of the Cholesky matrix factorization algorithm on a single-chip multiprocessor built on an APEX20K series FPGA developed by Altera. This multiprocessor system uses an asymmetric, shared-memory MIMD architecture, built using a configurable processor core called Nios, which was also developed by Altera. The whole system was developed on Altera's SOPC Development Kit using the Quartus 11 development environment.
The Cholesky algorithm is based on an algorithm described in George, et al. [9]. The key features of this algorithm are that it is scalable and uses a "queue of tasks" approach [9], which ensures dynamic load-balancing among the processing elements. The implementation also assumes dense matrices in the input.
Timing, speedup and efficiency results based on experiments run on uniprocessor and multiprocessor implementations are also presented.
Recommended Citation
Haridas, Satchidanand G., "FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture" (2003). Theses. 621.
https://digitalcommons.njit.edu/theses/621
