Document Type
Thesis
Date of Award
Spring 5-31-2004
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Roy H. Cornely
Second Advisor
Durgamadhab Misra
Third Advisor
Marek Sosnowski
Fourth Advisor
Leonid Tsybeskov
Abstract
Semiconductor random access memories are complex systems that can be described by performance parameters such as memory cycle time, access delays, storage capacity, bit packing density, chip area and retention time. In this thesis, tradeoffs between cycle time, chip area, and storage size as reflected by bit line capacitance (Cbl) were studied as a function of particular design variables: memory cell capacitance (Cc); CMOS flip-flop sense amplifier (SA) transistor sizes; and size of precharge (PC), and word line (WL) switches. Performance was optimized using circuit simulation software, HSPICE, to observe DRAM and SRAM waveforms. With TSMC 0.18 micron technology, minimum cycle times of 2.1 ins (DRAM) and 1.1 8ns (SRAM) were achieved (Cbl = 100FF), by optimizing the kr values of the SA transistors, for a fixed SA area of 1 micrometer and finding the optimum PC switch width (1 .6 micrometer). To maintain the same cycle time when the Cbl of both SRAM and DRAM increased by N, the required total chip area was found to be increased by N2. For a constant memory capacity, the ratio of the change in the sense amplifier area to the change in memory cycle time for DRAM was found to be between 1.25 to three times that of SRAM, varying somewhat with cycle time. To optimize SRAM cycle time, the criteria of a bit line difference of 10% of 3V determined the time to terminate the connection of the bit line to the SRAM cell so as to avoid the loading of the parasitic Cc cell by the larger Cbl.
Recommended Citation
Kale, Bageshri, "Study of design tradeoffs of DRAM and SRAM memories, using HSPICE computer simulation" (2004). Theses. 551.
https://digitalcommons.njit.edu/theses/551
