Document Type
Thesis
Date of Award
9-30-1986
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Michael Pratap Singh
Second Advisor
Peter Engler
Abstract
This thesis describes the method used for developing the standard TTL blocks using the logic simulator SPLICE1. It also gives a comprehensive overview of methods which can be used for designing a circuit which is testable. A format called Electronic Design Interchange Format (EDIF) is also described as a tool which can be used for transporting design data in the VLSI indgstry.
Recommended Citation
Mallampalli, Ravi Shankar Prasad, "Logic simulation and methodologies for design for testability" (1986). Theses. 3431.
https://digitalcommons.njit.edu/theses/3431
