Document Type
Thesis
Date of Award
5-31-1986
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Michael Pratap Singh
Second Advisor
Asghar Ibn Noor
Abstract
The aim of this thesis is to study and optimize the performance of NMOS sense amplifiers used in modern VLSI DRAMs.
Initially dynamic memory cells and popular sense amplifier circuits are surveyed.
A standard five transistor sense amplifier is later chosen for detailed analysis. Layout of the circuit is drawn to get the physical parameters. Using SPICE simulator, various effects of circuit parameters are studied. From these results optimal values of these parameters are arrived at.
Also an effort is made to derive theoretically equations for the latching time of a post amplifier which is the most important part in a sense amplifier.
Recommended Citation
Shah, Nimish K., "Design and optimization of NMOS sense amplifiers for VLSI DRAMS" (1986). Theses. 3379.
https://digitalcommons.njit.edu/theses/3379
