Document Type
Thesis
Date of Award
5-31-1987
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Yeheskel Bar-Ness
Second Advisor
Sol Rosenstark
Third Advisor
Joseph Frank
Abstract
Popular data compression schemes found in the literature are software based and present innumerable difficulties in hardware implementation. A data compression scheme, which can be directly implemented in hardware using systolic arrays, has been described. The scheme has a remarkable ability to 'adapt' itself to the changing statistics of the source file. Results generated after a comprehensive study and simulations of the algorithm have been presented. The scheme is inherently suitable for parallel processing. It can be incorporated in transmitting devices since it can be fabricated on a single VLSI chip. Comparison has been made with the LZW scheme. A quantised coding scheme which yields significant compression ratios when used with the Sliding Dictionary is presented. Arithmetic codes have also been used in conjunction with the scheme.
Recommended Citation
Nerurkar, Hemant L., "Hardware based data compression system using sliding dictionary algorithm" (1987). Theses. 3292.
https://digitalcommons.njit.edu/theses/3292
