Document Type
Thesis
Date of Award
5-31-1988
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
William N. Carr
Second Advisor
Michael Pratap Singh
Third Advisor
N. M. Ravindra
Abstract
This thesis presents the design of CMOS Static Random Access Memory (SRAM) which is imbedded within a high performance Programmable Logic Device (PLD). The SRAM and its control circuitry are used to initialize (or personalize) the NJIT PLD chip. The design is defined in 3-levels of functional hierarchy consistent with the physical and electronic design automation utilized for this design. The imbedded SRAM supports the PLD application circuit which includes 8 small Array and one large Control Programmable Logic Arrays.
The SRAM is structured as 64 X 138 bit array with serial read and write inputs. It is designed emphasizing simplicity of design and layout. The circuit design for the entire SRAM logic function is simulated with QUICKSIM. The basic storage cell contains 8 transistors and is replicated 8832 times throughout the array. The basic cell is designed with MOSIS CMOS 3 Micron DLM rules. The basic cell has been designed for optimizing silicon area, and the size of the basic cell is 96 microns X 76 microns. SPICE has been used to simulate the basic cell.
Recommended Citation
Vaidyanathan, Ravi K., "CMOS SRAM design for initializing programmable logic devices" (1988). Theses. 3228.
https://digitalcommons.njit.edu/theses/3228
