Document Type
Thesis
Date of Award
12-31-1988
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Marshall Chuan Yung Kuo
Second Advisor
John D. Carpinelli
Third Advisor
Yun Q. Shi
Abstract
This thesis has concentrated on some aspects of adaptive arrays, i.e., the data type as well as the calculating processes under an optimized version. An adaption of a modified bit-level array is described on the control structure for processes like correlation matrix, Q-R decomposition and solution of triangular linear systems. In short, an implementation of SMI(Sample Matrix Inversion) under a parallel systolic array process is consider5ed. Also an application of utilizing systolic array on a matrix inversion is derived. As a result, it could be predicted that a VLSI chip implementation for small adaptive arrays is feasible in the near future.
Recommended Citation
Tsai, Shin-Hwa, "An application of bit level systolic arrays on digitized adaptive array processes" (1988). Theses. 3224.
https://digitalcommons.njit.edu/theses/3224
