Document Type
Thesis
Date of Award
5-31-1988
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Michael Pratap Singh
Second Advisor
Joseph Frank
Abstract
This work studies in detail two dynamic logic families, namely Zipper and Nora. It compares their performance using SPICE, a popular circuit simulator. Results show that a novel clocking scheme and a different latch circuit for the Nora pipelined structure can push its maximum clock rate of CMOS Dynamic circuits higher. It also ascertains whether the increased complexity of NORA is justified compared to the simpler Zipper circuit. It is shown that for very long logic chains, Nora works faster than Zipper. The work also presents some guidelines for synthesis of logic functions using CMOS Dynamic Cells. It shows that standard cell based design will invariably result in increased chip area and decreased clock rate. It is proved that for a given technology, the full custom mixed NAND/NOR design performs better than the fixed NAND or fixed NOR cell based design.
Recommended Citation
Santurkar, Vinay, "Study of dynamic CMOS families and development of certain guidelines for logic synthesis" (1988). Theses. 3204.
https://digitalcommons.njit.edu/theses/3204
