Document Type
Thesis
Date of Award
5-31-1988
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
William N. Carr
Second Advisor
Michael Pratap Singh
Third Advisor
Roy H. Cornely
Abstract
This thesis develops a selected design database of gallium arsenide logic cells for automated design. Uniformly applied 1 um gate length physical layout rules are used for the design database with a standard cell design methodology.
Schottky Diode FET Logic (SDFL) technology with double level metallization was selected following a consideration of alternative gallium arsenide MESFET logic types. The SDFL approach is judged to provide improved noise margin, production yield, density, and lower power dissipation.
A cell library with 60 um cell height has been implemented with double entry for each cell input/output. Each cel1 has been simulated with SPICE 3B.1 circuit modeling based on process and device parameters considered to be standard. The noise margin (NM) for OR-based logic is 0.6 volt for the high state and 1.0 volt for the low state, respectively. The low state NM is found to degrade significantly to 0.5 volt for the dual-input NAND cell. The propagation delay of the inverter cell is 150 psec and 440 psec for the high-to-low (tPHL) and the low-to-high (tPLH) transitions, respectively. This stud48Hy shows that tPLH increases and tPHL decreases with increasing fan-in numbers. Both tPLH and tPHL increase when either the load capacitance or series load resistance increases. All pertinant operational parameters have been quantitatively determined and tabulated. The GDS II database has been captured using the Valid Logic Systems CAE software running on MicroVAX II workstations.
Recommended Citation
Liu, Nanchou, "Gallium arsenide standard cell CAD database for digital design" (1988). Theses. 3146.
https://digitalcommons.njit.edu/theses/3146
