Document Type
Thesis
Date of Award
5-31-1988
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Michael Pratap Singh
Second Advisor
Joseph Frank
Abstract
In order to acheive higher performance in a pipeline processor, proper interrupt handling is essential. In a pipeline processor, interrupt handling is difficult because many instructions are in the processor at the same time. This study describes and evaluates the different solutions to interrupt handling. Several pipelined 32-bit microprocessors have also been studied and their architectural and programming features are compared.
Recommended Citation
Gami, Shailesh Ratilal, "An investigation of interrupt handling schemes in pipeline processors" (1988). Theses. 3076.
https://digitalcommons.njit.edu/theses/3076
