Document Type
Thesis
Date of Award
5-31-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
William N. Carr
Second Advisor
Kenneth Sohn
Third Advisor
N. M. Ravindra
Abstract
This thesis describes the design including specification, schematics,logic and circuit simulation, and standard cell layout for a CMOS mixed-mode I.C. for interfacing sensors into a robotics local area network. The network accepts up to 256 interface chips as nodes in each area. A simple network protocol permits acquisition of digital data from the interface nodes through gateways into ARCNET and MAP.
The sensor chip interfaces directly from analog signals of range 0-1V and 0-20mV. It contains an 8-bit ADC. The application I.C. interfaces to sensors for pressure, tactile stress, humidity, temperature, etc.
Each of the sensor interface node I.C.s is assigned a unique 8-bit I.D. using a DIP switch ( later an EEPROM could be designed in ). The gateway interface I.0. controls the network polling using a photonic manchester code at a nominal 500 bps rate. The sensor chip uses a clock derived from a RC oscillator.
The sensor interface chip contains a ADC which uses a switched capacitor array and a successive approximation register(SAR) technique. A handgap reference voltage generator is used in the ADC. Data input to the IC is derived from a photocliode.
The calculated analog power dissipation is 5.42mW. The digital circuits dissipate 8.11iW for 1 KHz clock. The circuit was simulated by using UC Berkeley SPICE 20.5. Physical layout is clone with the Mentor Graphics/ Apollo workstation network. Layout uses the NET CMOS3 standard cell library and is based on a 3p, CMOS double-poly and single-metal technology. The final chip size is 4.0mm x 3.5mm including bonding pads.
Recommended Citation
Kim, Yong-Bin, "A CMOS robotic lan interface integrated circuit design" (1989). Theses. 2819.
https://digitalcommons.njit.edu/theses/2819
