Document Type
Thesis
Date of Award
8-30-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Asghar Ibn Noor
Second Advisor
Michael Pratap Singh
Abstract
Generating a set of test vector for a digital circuit is the most critical step in design and test. It is very important to generate test sequence easily and efficiently. The importance is enhanced by the fact that the simulation database is being used to create test programs. A CAD tool ATPG (Automatic Test Pattern Generator) has been developed to specify and satisfy requirements of designers and test engineers. EDIF (Electronic Design Interchange Format) is followed closely. EDIF targets compatability among foundry services and CAD/CAE systems.
Recommended Citation
Khan, Mohammad Akram, "A CAD for edif pattern generation" (1989). Theses. 2816.
https://digitalcommons.njit.edu/theses/2816
