Document Type
Thesis
Date of Award
6-30-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
William N. Carr
Second Advisor
Durgamadhab Misra
Third Advisor
John D. Carpinelli
Abstract
An application specific integrated circuit has been designed for use as a gateway between two local area networks. This silicon chip provides the gateway function to link the NJIT robotics network and the MAP IEEE-standardized network. This IC utilizes the available Motorola MC 68824 Token Bus Controller for the MAP data path. A special IO design compatible with an optical communication link is used to interface into the NJIT RLAN network.
The gateway IC serves as an asynchronous buffer between the 5Mbps MAP link and the 500 bps local optical link. The control protocol provides the master function for polling upto 255 sensor nodes with a reconfiguration and a unique data packet. The design is almost totally automated following the design specification and schematic circuit capture. A Mentor Graphics Corp. turnkey workstation environment on an Apollo platform using a standard cell based methodology is used. A total of 21 cells are used from the cell library. Automatic placement and routing is used to create the IC which contains 1744 nets and 1722 cells. The technology used for the chip is single-level polysilicon, single-level metal CMOS with a 3 micron critical dimension. The final compacted chip layout measures 6.14u 6.16 m m2 including wire bonding pads.
Recommended Citation
Joshi, Jayesh M., "Design of robotic LAN controller and map interface" (1989). Theses. 2794.
https://digitalcommons.njit.edu/theses/2794
