Document Type
Thesis
Date of Award
6-30-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
William N. Carr
Second Advisor
Durgamadhab Misra
Third Advisor
N. M. Ravindra
Abstract
This research delineates a test strategy and detailed sequence of test vectors for a new class of programmable logic devices (PLDs). This new class of devices is based on architectures that contain programmable logic arrays (PLAs) programmed by on chip integrated static RAMs or EEPROMS. The new PLD architecture poses unique testing problems which require 100% nodal test coverage. Previous PLAs/PLDs did not require that 100% of the nodes be tested since their circuits utilized fuse link crosspoints and were not dynamically reprogrammable. Such devices could be tested by a unique personality pattern that combined the application and the test circuit. The new PLA/PLD architecture requires testing of arbitrary personality patterns. The dynamic reprogrammability of these devices presents a more challenging 100% test requirement. The same PLA/PLD device can be reconfigured for many different personality patterns permitting a 100% internal node coverage using externally applied test stimulus-response sequences at the packaged device's pins.
This work details the testing of a specific PLA/PLD circuit but attempts to provide a scheme of general applicability. All stuck at, bridge and crosspoint faults are tested. The unified testing scheme minimizes the costs for both the production and application environments.
Recommended Citation
Chopra, Arvind, "Optimal algorithmic testing of re-programmable logic arrays" (1989). Theses. 2749.
https://digitalcommons.njit.edu/theses/2749
