Document Type
Thesis
Date of Award
5-31-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Michael Pratap Singh
Second Advisor
Tushar Bhattacharjee
Abstract
New CMOS dynamic latches are designed which can be used along with conventional dynamic circuits to realize fast pipelined dynamic logic. Also a new method is described for detecting the difficult CMOS Non-classical faults viz. stuck open and stuck on faults. The conventional Domino logic is redesigned to make all the stuck open and stuck on faults detectable.
Recommended Citation
Arunachalum, Ashok, "Performance enhancement & fault detection of CMOS dynamic logic for VLSI" (1989). Theses. 2721.
https://digitalcommons.njit.edu/theses/2721
