Document Type
Thesis
Date of Award
12-31-1991
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Sotirios Ziavras
Second Advisor
John D. Carpinelli
Third Advisor
Edwin Hou
Abstract
The extensive development of large-scale digital computers has naturally been accompanied by a corresponding development of techniques for fast arithmetic operations. Addition is the basis for the majority of the other arithmetic operations and most of the required time is due to carry propagation delay. Various algorithms have been proposed for fast addition and multiplication. The algorithms proposed here use the redundant binary system and are designed for the mesh structure. The algorithms are very efficient for the addition and multiplication of long operands. The algorithms can also be implemented on the hypercube. The n-dimensional hypercube is a highly concurrent loosely coupled multiprocessor which is based on the binary n-cube topology. Algorithms for the hypercube may be very fast due to its powerful interconnection network. The hypercube supports both regular and irregular communications with the capability of effectively emulating a large variety of other frequently used structures, like rings, trees, meshes, pyramids, etc. The proposed algorithms operate in the SIMD mode. The redundant binary system limits carry propagation to one position to the left during the operation of addition and subtraction. Thus, carry propagation chains are eliminated with the use of the redundant binary system. Redundancy in the number representation allows a method of fast addition and subtraction in which each sum digit is the function of the digits in two adjacent positions of the operands. The total delay is independent of the size of the operands and hence very large sized operands can be added with only two steps. one to obtain the intermediate result and another one to find the final result. The computation time is 2q + 1 "cycles", where q is the number of bits of each operand stored in each processor. The mechanism that converts from the standard binary to the redundant binary system takes 1 cycle. The reverse conversion is a very time consuming process applied to the result. It uses a conditional sum technique in which the last step is sequential. The time complexity of this semi-parallel scheme is q + nproc, where nproc is the total number of processors in the system. The proposed multiplication algorithm is based on the parallel addition algorithm discussed earlier; partial products are first generated and then added pairwise. The proposed algorithms were simulated on a VAX 8530/8800 machine and were compared with more conventional algorithms. Performance results are presented for the purpose of comparison.
Recommended Citation
Rana, Anil, "Realization of high-speed carry propagation for addition and multiplication using the redundant binary system on the mesh and hypercube connected structures" (1991). Theses. 2603.
https://digitalcommons.njit.edu/theses/2603
