Document Type
Thesis
Date of Award
1-31-1991
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Wei Chen
Second Advisor
Durgamadhab Misra
Third Advisor
N. M. Ravindra
Abstract
The primary benefits of VLSI chips are their high speed, small area, and lower power. These performance attributes are dependent on the quality of chip design. As a result, performance can be optimized by proper design decisions. One of the decisions in chip design is the selection of gate delays and/or transistor sizes (channel width of an MOS transistor).
To optimize the performance of VLSI chips, transistor delay models and optimization algorithms are very important since accurate analytical models for signal delay are essential to replace expensive device level simulation and the high efficient algorithms assist designers in developing high performance VLSI circuits.
The high performance VLSI circuits can be obtained by identifying and optimizing delay in the critical path. A timing analyzer and a circuit simulator are used to evaluate the delay time. The methods used in EO and TILOS are two typical approach to optimize circuit delay. The method used in Electric Optimizer (EO) [1] can be used to optimize larger circuits interactively and calculate optimum speed or power transistor sizes for set of paths through the circuit subject to constraints on the minimum and maximum transistor sizes. The other method used in Timed Logical Sythesizer (TILOS) [4] is more advanced than other previous methods. The optimization is conducted by iteration. Specifically, at each iteration, the delay information reported by timing analyzer is examined and a set of critical transistors is selected.
From a computational point of view, there are three drawbacks in these approaches. 1) Delay time is dependent on circuit simulation or a timing analyzer. Especially, when the number of transistors is increased, simulation time is rapidly increased. 2) Parameters are changed by designers. It lacks an efficient way to get a good transistor parameter. 3) Delay optimization is restricted on the gate or transistor level rather than hierarchical circuit.
The goal of this thesis is to optimize transistor sizes so that the time delay in CMOS VLSI circuits is optimized. To achieve this, an algorithm was developed which can be used to optimize automatically hierarchical circuits. The algorithm has been implemented in C programming language. The program is called HOT (Hierarchical Optimization of Time delay). It optimizes transistor size in the critical path by iteratively adjusting parameters until the minimum time delay was identified. The algorithm described in this thesis performs a reasonable amount of delay optimization without seriously affecting the power or area in hierarchical circuit or system. The preliminary results indicate that this approach can improve both the delay and response characteristics of the circuits.
Recommended Citation
Quan, Yumei, "HOT : a timing optimizer for hierarchical VLSI circuits using the charge conservation delay model" (1991). Theses. 2601.
https://digitalcommons.njit.edu/theses/2601
