Document Type
Thesis
Date of Award
5-31-1991
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
William N. Carr
Second Advisor
John D. Carpinelli
Third Advisor
Edwin Hou
Abstract
This thesis presents a novel algorithmic approach which can be used to reduce the total test pattern lengths for testing a sequential logic circuit. Test generation for sequential circuits has long been recognized as a difficult task. Several approaches have been made in the past to solve the problems of test generation stage for sequential circuits but they were either an extension of the classical D-algorithm or based on the random techniques. When number of states of the sequential circuit is larger and the test demands long input sequences, they can be quite ineffective for the test generation. The STALLION algorithm handles the problem of generating tests for faults that require a lengthy input sequence very efficiently by extracting a partial state transition graph and using it in conjunction with fault excitation-and-propagation and state justification algorithms. An efficient algorithmic test generation such as using STALLION is not adequate alone because the generated test patterns are not optimized for running test. The proposed formatting algorithm TEPMIL is used in conjunction with automatic test pattern generators. The TEPMIL algorithm operates on the test patterns created by automatic test patterns generators and formats them in an optimal sequence. Use of these formatted test patterns can reduce time for running test.
Recommended Citation
Patel, Chetan, "Minimized test patterns for sequential logic" (1991). Theses. 2577.
https://digitalcommons.njit.edu/theses/2577
