Optimization of a 3-micron BCCD process for high density CCD registers

Author

Mark Ratner, New Jersey Institute of Technology

Document Type

Thesis

Date of Award

5-31-1992

Degree Name

Master of Science in Electrical Engineering - (M.S.)

Department

Electrical and Computer Engineering

First Advisor

Walter F. Kosonocky

Second Advisor

Kenneth Sohn

Third Advisor

Durgamadhab Misra

Abstract

In July 1991, Dr. Walter F. Kosonocky proposed a High-Frame-Rate-CCD Imager. The design of the imager is such that the CCD channel width be 3-microns and capable of handling at least 3000 - 5000 electrons per square micron. Using process (SUPREM III) and device (PISCES IIB) simulations, charge handling capacities as a function of implant energy and junction depth were studied. Arsenic implants ranging from 100 to 200keV were driven-in to obtain junction depths between 0.40µm and 0.80µm. As a result of this work it was determined that charge handling capacities as high as 9400 electrons/µm² were achievable with implanted doses of 1.6E12 ions/cm². This thesis is a description of the simulation and analysis techniques used to optimize the charge handhng capacity of a 31.1m wide BCCD channel.

Recommended Citation

Ratner, Mark, "Optimization of a 3-micron BCCD process for high density CCD registers" (1992). Theses. 2337.
https://digitalcommons.njit.edu/theses/2337