Document Type
Thesis
Date of Award
1-31-1993
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Durgamadhab Misra
Second Advisor
Lonnie R. Welch
Third Advisor
Walter F. Kosonocky
Abstract
This work describes a novel VLSI implementation of the Architecture for Reusable Components (ARC) processor, using Hardware Description Language (HDL). The main goal here is to achieve efficient execution of reusable software through proper hardware support. This involves the hard wired implementation of each instruction designed for the ARC processor.
Instructions are broken down into their logical functions, then modeled and simulated through the hierarchical design methods that HDL offers. The structural model of the processor has been developed and simulated. The purpose here has been to begin work on the design and implementation of the ARC processor.
The instructions were built using HDL modules, and then simulated using a logic simulator. The effect of internal propagation delays in the execution of the logic modules have been investigated. Changes in delay parameters have been applied to obtain correct logic transfer operations. The redundancy in the logic transfer operations have also been investigated to see parallelism at the instruction execution level.
Recommended Citation
Kakadasam, Deepak, "Partial VLSI implementation of the architecture for reusable components (ARC)" (1993). Theses. 1780.
https://digitalcommons.njit.edu/theses/1780
